A sensor element disclosed in “DEVICE AND METHOD FOR THE DETECTION AND DEMODULATION OF AN INTENSITY-MODULATED RADIATION FIELD (see patent literature (PTL) 1)” published in 1994, or in other documents, which has a function for modulating, in a time domain, the detection of electrons generated by light in a pixel, is referred to as a “lock-in pixel”. By applying the sensor element encompassing the lock-in pixels to a buried photodiode structure used in recent CMOS image sensors, if a lock-in image sensor can be established, because the sensor element is superior in mass productivity, a realization of a high performance image sensor being manufactured at low price is expected.
For example, a three-dimensional imaging system including a two-dimensional array implemented by pixel-photo detectors, dedicated electronic circuits and corresponding processors, which are merged in a common IC, by using a CMOS manufacturing technique, is proposed (see PTL 2). In one embodiment of PTL 1, each detector has a corresponding high-speed counter for accumulating the number of clock pulses that is proportional to a time of flight (TOF) about pulses, which are radiated by the system, reflected from a point of a physical body, and focused, and then detected by the pixel-photo detector. A TOF data gives a direct digital scale with regard to a distance between the particular pixel and the point on the physical body for reflecting the radiated optical pulse. In a second embodiment of PTL 2, the counter and a high-speed clock circuit are not provided. Instead of them, a charge accumulator and an electronic shutter (S1) are provided in each pixel detector. Each pixel detector accumulates charges, and its total amount gives the direct scale of the round-trip TOF.
However, in the conventional image sensors that use the lock-in pixels, each of the lock-in pixels detects transferring-operations of charges to one or more accumulation regions, through a gate structure of a MOS transistor, in synchronization with the modulated light. Consequently, the conventional image sensor that uses the lock-in pixels is intricate in structure. Also, in the case of the transfer through the gate structure of the MOS transistor, electrons are captured in traps at a boundary between silicon (Si) and silicon oxide film (SiO2), and a problem of transfer delay is also generated.
Consequently, one of the inventors proposed a structure in which a semiconductor element serving as each of the pixels in a solid-state imaging device encompassing a light-receiving surface-buried region of n-type to which light is entered; a charge accumulation region of n-type, being buried at a position partially overlapping with the light-receiving surface-buried region, in a planar pattern, and is deeper in potential well (electron well) than the light-receiving surface-buried region, configured to accumulate charges generated by the light-receiving surface-buried region; a charge-read-out region of n-type, configured to receive charges accumulated in the charge accumulation region; and first and second extracting-drain regions of n-type, which are arranged on both sides of the light-receiving surface-buried region, respectively, on the planar pattern, so as to extract electrons generated by the light-receiving surface-buried region (see PTL 3). Here, the light-receiving surface-buried region and the first and second extracting-drain regions are buried in a part of a surface of a semiconductor region of p-type. On the light-receiving surface-buried region, a p+-type pining layer is arranged. On the p+-type pining layer, on the semiconductor region between the p+-type pining layer and the first extracting-drain region, and on the semiconductor region between the p+-type pining layer and the second extracting-drain region, gate insulation films are formed. Then, on the gate insulation films, in order to extract electrons generated by the light-receiving surface-buried region to the first and second extracting-drain regions, respectively, first and second extraction-gate electrodes are arranged, on both sides of the light-receiving surface-buried region, so as to sandwich the light-receiving surface-buried region, on the planar pattern.
In the structure disclosed in PTL 3, between the charge accumulation region and the charge-read-out region, a read-out gate electrode for transferring charges to the charge-read-out region from the charge accumulation region is arranged, and the read-out gate electrode controls a potential of a transfer channel formed between the charge accumulation region and the charge-read-out region through a gate insulation film so as to transfer charges from the charge accumulation region to the charge-read-out regions. The combination of the gate insulation film and the first and second extraction-gate electrodes on the gate insulation film controls the potential of a channel formed in the upper portion of the semiconductor region between the light-receiving surface-buried region and the first extracting-drain region, and the potential of a channel formed in the upper portion of the semiconductor region between the light-receiving surface-buried region and the second extracting-drain region, respectively, so as to extract charges from the light-receiving surface-buried region to the first and second extracting-drain regions, respectively.
According to the structure disclosed in PTL 3, even if a gate structure is not provided between the light-receiving surface-buried region and the charge accumulation region, it is possible to control the transferring of charges from the light-receiving surface-buried region to the charge accumulation region, by changing potential profiles on the basis of voltages applied to the first and second extraction-gate electrodes.